FPGA Generated Lissajous Curves

In a normal graph, the data (or signal) is plotted against time. If the signal is a time-varying sinusoid, then you’ll see a sine wave against time on the plot. If, however, you plot a sinusoidal signal against another sinusoidal signal (i.e. installing of a Y-Time plane you have a Y-X plane), you can generate what are known as “Lissajous curves”. The shape of these curves is dependent upon the ratio of the frequencies of the two sinusoids and the phase difference between them. If you want to read more about these curves, Wikipedia has a good overview of them: https://en.wikipedia.org/wiki/Lissajous_curve

I recently wanted to start playing around with FPGAs again, so I bought a CMOD A7-15T development module. It is an Artix-7 15T FPGA onboard (for those that are interested in the specs, the 15T has 10400 LUTs, 20800 Flip-Flops and 122.5 kB of block RAM). For fun, I wanted to generate some Lissajous curves using the FPGA. To do this, I breadboarded two 8-bit R-2R ladder DACs and connected them to the pins on the development module. The code for this project was written in VHDL. I setup two 256-point look up tables (implemented in block ram), each with a different frequency sinusoid. I then had a wave gen module that incremented a counter when a clock event occurred and this counter was used to index into the look up tables. The output of these LUTs was then tied to GPIOs which were connected to the DACs. The RTL schematic is shown below:

And here is the FPGA and the two R-2R ladder DACs:

Using this setup I firstly generated some Lissajous signals using a frequency ratio of 2:1, with no phase offset. I set my digital oscilloscope (the Rigol DS1054Z) in X-Y mode to plot the curve, and I also setup my CRO (a 40MHz Hameg) to do the same thing. The pictures are shown below. Don’t they look cool!

In Australia, the idea for the Australian Broadcasting Corporation’s logo came from a 3:1 Lissajous curve. So I decided to generate a 3:1 curve to try and replicate the ABC logo. As you can see below, what I got was definitely not the ABC logo!

After a quick hop trip to Wikipedia, I discovered that the logo is in fact generated by a 3:1 curve with a 90 degree phase offset! After adjusting the look up tables with this offset, I managed to get the logo seen below:

Which looks really cool! Why did I do this you may ask? Well I just wanted to do something cool to get back into the swing of using VHDL. Stay tuned for some more FPGA related stuff!